1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, specifically to a manufacturing method of a semiconductor device having a through-hole electrode.
2. Description of the Related Art
A CSP (Chip Size Package) has received attention in recent years as a three-dimensional mounting technology as well as a new packaging technology. The CSP means a small package having about the same outside dimensions as those of a semiconductor die packaged in it.
A BGA type semiconductor device with a through-hole electrode has been known as a kind of CSP. This BGA type semiconductor device has a through-hole electrode that penetrates through a semiconductor substrate and is connected with a pad electrode. And a plurality of ball-shaped conductive terminals made of metal such as solder is arrayed in a grid pattern on a back surface of the semiconductor device.
When the semiconductor device is incorporated into electronic equipment, each of the conductive terminals is connected to a wiring pattern on a circuit board such as a printed circuit board.
Such a BGA type semiconductor device has advantages in providing a large number of conductive terminals and in reducing size over other CSP type semiconductor devices such as an SOP (Small Outline Package) and a QFP (Quad Flat Package) that have lead pins protruding from their sides.
Next, a conventional manufacturing method of the BGA type semiconductor device with the though-hole electrode will be described referring to the drawings. FIGS. 24-27 are cross-sectional views showing the conventional manufacturing method of the semiconductor device.
First, a pad electrode 52 is formed on a top surface of a semiconductor substrate 50 through a first insulation film 51, as shown in FIG. 24. Next, a supporting body 54 is bonded to the top surface of the semiconductor substrate 50 through a resin layer 53, when necessary.
Next, a second insulation film 55 is formed on a back surface of the semiconductor substrate 50 and a photoresist layer 80 is selectively formed on the second insulation film 55. The photoresist layer 80 has an opening at a location corresponding to the pad electrode 52. A via hole 56, which penetrates through the semiconductor substrate 50 and the second insulation film 55 and exposes the first insulation film 51, is formed by etching the second insulation film 55 and the semiconductor substrate 50 using the photoresist film 80 as a mask.
Furthermore, the first insulation film 51 exposed at a bottom of the via hole 56 is removed by etching using the photoresist layer 80 as a mask, as shown in FIG. 25.
Next, a third insulation film 57 is formed on a surface of the via hole 56 and on the second insulation film 55, as shown in FIG. 26.
Then the third insulation film 57 on the bottom of the via hole 56 is removed by etching from the back surface of the semiconductor substrate 50 to expose the pad electrode 52, as shown in FIG. 27.
Furthermore, a through-hole electrode (not shown) that is connected with the pad electrode 52 is formed in the via hole 56. And a wiring layer (not shown) connected with the through-hole electrode is formed on the back surface of the semiconductor substrate 50. A protection layer (not shown) is formed over the back surface of the semiconductor substrate 50 including the wiring layer. Then a portion of the protection layer is removed to expose a portion of the wiring layer, and a conductive terminal (not shown) is formed on the portion of the wiring layer. After that, the semiconductor substrate 50 is separated into a plurality of semiconductor dice by dicing.
Further description on the technologies mentioned above is disclosed in Japanese Patent Application Publication No. 2003-309221, for example.
In the conventional manufacturing method of the semiconductor device described above, however, the third insulation film 57 is formed after the pad electrode 52 is exposed by etching the first insulation film 51 on the bottom of the via hole 56 as shown in FIG. 25, and then the pad electrode 52 is exposed once again by etching the third insulation film 57 on the bottom of the via hole 56 as shown in FIG. 27. That is, two times of etching are required to expose the pad electrode 52 at the bottom of the via hole 56 while keeping the third insulation film 57 on a side wall of the via hole 56.
In addition, there is a problem that corners of the semiconductor substrate 50 are exposed at the bottom of the via hole because of convergence of electric field and over etching at the corners during the etchings to remove the first insulation film 51 and the third insulation film 57 on the bottom of the via hole 56. As a result, insulation failure is caused later between the through-hole electrode (not shown) formed in the via hole 56 and the semiconductor substrate 50.
In order to avoid the insulation failure between the through-hole electrode and the semiconductor substrate 50, the etchings must be controlled very carefully so that amounts of etching of the first insulation film 51 and the third insulation film 57 are kept as small as possible, while the pad electrode 52 is securely exposed. This makes process in the manufacturing method of the semiconductor device complicated, raising a problem of increased manufacturing cost.
And when the etching of the first insulation film 51 is insufficient, there arises a problem of electrical connection failure between the pad electrode 52 and the through-hole electrode (not shown) to be formed in the via hole 56. This reduces yield of the semiconductor device.